-- This model is based on
-- http://members.aol.com/vhdlcohen/vhdl/vhdlcode/switch1.vhd
-- and therefore the following copyright statement is valid:

------------------------------------------------------------------------
-- Copyright (c) 1997, Ben Cohen.   All rights reserved.
-- This model can be used in conjunction with the Kluwer Academic book
-- "VHDL Coding Styles and Methodologies", ISBN: 0-7923-9598-0
-- "VHDL Amswers to Frequently Asked Questions", Kluwer Academic
-- which discusses guidelines and testbench design issues.
--
-- This source file for the switch model may be used and
-- distributed without restriction provided that this copyright
-- statement is not removed from the file and that any derivative work
-- contains this copyright notice.
------------------------------------------------------------------------

------------------------------------------------------------------------
-- Author: Ralf Hildebrandt - Ralf-Hildebrandt@gmx.de
------------------------------------------------------------------------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;


------------------------------------------------------------------------
entity transfergate is
generic(
        chain_length			        : positive:=5 );                -- number of transfergates in a chain - don't set too high
port(
        wireA,wireB                             : inout std_logic;
        enable                                  : in    std_ulogic );
end transfergate;
------------------------------------------------------------------------


architecture behavior of transfergate is

begin

------------------------------------------------------------------------
process
variable	last		: time;
begin
wait on wireA'transaction, wireB'transaction, enable'transaction until last/=now;
last:=now;
wireA<='Z'; -- remove driver of transfergate
wireB<='Z'; -- remove driver of transfergate
wait for 0 ns; -- wait for a delta cycle
if (enable='1') then
	for N in 2 to chain_length loop
		if (wireA='Z' AND wireB='Z') then
			wait for 0 ns;
		end if;
		-- If a signal has to propagate through a chain of transfergates
		-- the 1st gate drives 'Z' after a delta delay and therefore the
		-- next gates sees 'Z'.
		-- So, wait for another delta delay, to wait for the 1st gate
		-- to drive the bus and then evaluate again.
	end loop;
	wireA<=wireB; -- transfergate drives with the values, now seen on the bus
	wireB<=wireA; -- transfergate drives with the values, now seen on the bus
end if; -- no else 'Z' nessecary - already done
end process;
------------------------------------------------------------------------


end behavior;